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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:34:07 11/23/2017 
-- Design Name: 
-- Module Name:    ajxd - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ajxd is
    Port ( clk : in  STD_LOGIC;
           keyi : in  STD_LOGIC;
           keyo : out  STD_LOGIC);
end ajxd;

architecture Behavioral of ajxd is
signal cnt: integer range 0 to 20:=1;
begin


process(clk,keyi)
begin

 if keyi='0' then
    keyo<='0';
    cnt<=1;
elsif clk'event and clk='1' then
    if cnt=5 then
       keyo<='0';
      --   cnt<=1;
    else
       keyo<='1';
       cnt<=cnt+1;
     end if;
-- end if;
end if;
end process;
end Behavioral;


